Verilog Woes

As a language, Verilog is decent. It's a little too low level for my tastes, which is why I used to use Cryptol and now use my employer's fork of Cryptol called Quattro. Cryptol/Quattro allow us to write much more abstract, generic, and parametrized code, and to do so usually with no loss in performance.

Then there's the inconsistencies between simulation and synthesis tools, especially if your tools come from different companies. A language construct might be supported by your simulation tool but not your synthesis tool, or vice versa.

And then there's the case where your tool just does something batty. For example, lets say that I have an integer parameter P in module A, and I a string parameter P in module B, and I want to instantiate B inside A and have A's parameter determine B's parameter. So, I have something like this:

defparam B_inst.P = (P == 0) ? "TRUE" : "FALSE";

Fine and dandy right?

For whatever reason, my Verilog simulator decided that the two branches of the expression, the two strings, had to be the same length. So, it padded "TRUE" with a space at the beginning to become " TRUE". I did a lot of experimenting to verify that this is in fact what is happening. For example, if I change "FALSE" to a string of 4 characters when P is 0, it works fine.